An embodiment of the invention is generally related to the testing of high-speed data links, and in particular to determining robustness of link interface circuitry in the presence of jitter. Other embodiments are also described and claimed.
As the bit rate of a high-speed data link increases, its testing becomes more challenging. For example, recent advances in serial, point to point data links for integrated circuit input/output (or simply, chip I/O) are calling for bit streams at upwards of several GHz. At such high speeds, external test probes can disturb the transmission medium of the link and hence distort the test results. Accordingly, on-chip, built-in self-test techniques have been proposed, to test the link as a whole while it is operating “at speed”, including the transmission medium and the chip I/O interface circuitry used in the link. In one such technique, a predefined test pattern transmitted by the chip is looped back to a receiver in the chip. The receiver recovers a sequence of bits that are compared with the test pattern, to determine any error.
With higher operating frequencies often comes a smaller margin for error. At higher operating speeds, a data link tolerates a smaller variation from its nominal design specification. Such variations may be caused by manufacturing/real world limitations in the transmission medium and link interface circuitry (e.g., driver and sampler termination mismatches relative to the line characteristic impedance; noise couplings; inter-symbol interference, etc.) Built-in self-test techniques have been developed that “stress” the link during operation, to determine its robustness or tolerance to such variations. This is also referred to as margining the link or determining the link's margin for error. In one such technique, a timing variation referred to as jitter is forced into the transmitter of the link. A transmitted signal carrying the clocked test bits is thus jittered, to exhibit certain forced time shifts. The effect of this jitter at the receiver is then evaluated, by determining whether the sequence of bits recovered by the receiver is the same as the transmitted one. The injected jitter is gradually worsened during the test until an error is detected, thereby giving a measure of the margin for error.